Iwata's web page

Contact

Associate Professor, National Institute of Technology (KOSEN), Nara College

Name

Ph.D. Hiroshi Iwata

Address

22 Yata, Yamato-Koriyama, Nara 639-1080, Japan

Email

Education

• A.S., Information Technology, Nara National College of Technology (Mar. 2005)
• B.E., National Institution for Academic Degrees and University Evaluation (Mar. 2007)
  (Nara National College of Technology Faculty of Advanced Engineering, Information Engineering)
• M.E., Nara Institute of Science and Technology, Graduate School of Information Science (Sep. 2008)
• Ph.D., Nara Institute of Science and Technology, Graduate School of Information Science (Mar. 2011)

Jobs

• Assistant Professor, Department of Information Engineering, Nara National College of Technology (Apr. 2011)
• Assistant Professor, Department of Information and Computer Engineering, National Institute of Technology, Kisarazu College (Apr. 2016)
• Lecturer, Department of Information Engineering, National Institute of Technology, Nara College (Apr. 2018)
• Associate Professor, Department of Information Engineering, National Institute of Technology, Nara College (Apr. 2020)

Research

Journal paper

1. Hiroshi Iwata, Satoshi Ohtake and Hideo Fujiwara: ``A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification,'' IEICE Transactions on Information and Systems, Vol. E93-D, No. 7, pp. 1857-1865, July 2010.
2. Hiroshi Iwata, Nanami Katayama and Ken'ichi Yamaguchi: ``Formal Verification-Based Redundancy Identification of Transition Faults with Broadside Scan Tests,'' IEICE Transactions on Information and Systems Vol.E100.D, No.6, pp.1182-1189, Jun. (2017)
3. Takashi Koga, Ken'ichi Yamaguchi, Hiroshi Iwata, and Ikusaburo Kurimoto: ``Kriging Interpolation for Vapor Pressure Deficit in Plant Factory with Solar Light,'' Proceedings of the SICE Annual Conference 2019, pp.1000-1003, Sep. 2019.

International Conference

1. Hiroshi Iwata, Satoshi Ohtake and Hideo Fujiwara: ``An approach to RTL-GL path mapping based on functional equivalence,'' 9th IEEE Workshop on RTL and High Level Testing (WRTLT'08), pp. 63-68, 2008.
2. Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata and Hideo Fujiwara: ``Optimizing Delay Quality with a Limited Size of Test Set,'' Proc. IEEE International Workshop on Reliability Aware System Design and Test, pp.46-51, Jan. 2010.
3. Hiroshi Iwata, Satoshi Ohtake and Hideo Fujiwara: ``Enabling False Path Identification from RTL for Reducing Design and Test Futileness,'' The 5th IEEE International Symposium on Electronic Design, Test & Applications (DELTA 2010), pp.20-25, Jan. 2010.
4. Satoshi Ohtake, Hiroshi Iwata and Hideo Fujiwara: ``A synthesis method to propagate false path information from RTL to gate level,'' The IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems 2010, pp.197-200, Apr. 2010.
5. Michiko Inoue, Akira Taketani, Tomokazu Yoneda, Hiroshi Iwata and Hideo Fujiwara: ``Test Pattern Selection to Optimize Delay Test Quality with a Limited Size of Test Set,'' 15th IEEE European Test Symposium (ETS'10), pp.260, May. 2010.
6. Hiroshi Iwata, Satoshi Ohtake, Michiko Inoue and Hideo Fujiwara: ``Bipartite Full Scan Design: A DFT Method for Asynchronous Circuits,'' IEEE 19th Asian Test Symposium (ATS'10), pp.206-211, Dec. 2010.
7. Hiroshi Iwata, Sayaka Satonaka and Ken'ichi Yamaguchi: ``An Efficient Test Pattern Generator -Mersenne Twister- ,'' The 18th Workshop on Synthesis And System Integration of Mixed Information Technologies, R1-12, pp.62-67, Oct. 2013.
8. Ryo Ogawa, Hiroshi Iwata and Ken'ichi Yamaguchi: ``Threshold Power-Aware Test Pattern Ordering for Deterministic Circular Self Test Path,'' 14th IEEE Workshop on RTL and High Level Testing, III.5.S, pp.1-4, Nov. 2013.
9. Shin'ya Ueoka, Hiroshi Iwata and Ken'ichi Yamaguchi: ``Tree-focused Graph Bipartition for Asynchronous L1L2* Scan Design,'' 14th IEEE Workshop on RTL and High Level Testing, IV.3.F, pp.1-6, Nov. 2013.
10. Yuko Kakazu, Hiroshi Iwata, Ikusaburo Kurimoto and Daichi Moriuchi: ``Development of the Handy Type LIF System,'' Proceedings of the SICE Annual Conference 2018, ThCPo03.4, pp.1267-1268, Sep. 2018.
11. Hiroshi Iwata and Ikusaburo Kurimoto: ``Active Sensing Platform for Mathematical Analysis in Plant Factory with Solar Light,'' Proceedings of the SICE Annual Conference 2018, ThCPo03.6, pp.1273-1275, Sep. 2018.
12. Takashi Koga, Ken'ichi Yamaguchi, Hiroshi Iwata, and Ikusaburo Kurimoto: ``Kriging Interpolation for Vapor Pressure Deficit in Plant Factory with Solar Light,'' Proceedings of the SICE Annual Conference 2019, pp.1000-1003, Sep. 2019.
13. Chihiro KAGEYAMA, China SASAKI, Hiroshi IWATA, Yosuke ASANO, Yuichi ITOH, and Ikusaburo KURIMOTO: ``Construction of Spatial H2O/CO2 Measurement IoT System for Sunlight Type Plant Factory,'' Proceedings of the SICE Annual Conference 2020, pp.1921-1923, Sep. 2020.
14. Haruki Chaen, Ken'ichi Yamaguchi and Hiroshi Iwata: ``A Proposal of Identification Method for Second-Generation Redundancy Fault,'' 21st IEEE Workshop on RTL and High Level Testing, TS1-2, pp.1-2, Nov. 2020.
15. Yuta Shintani, Ken'ichi Yamaguchi and Hiroshi Iwata: ``An Implementation of Functional Speed Oriented Transistor-Level Scan C-element,'' 21st IEEE Workshop on RTL and High Level Testing, TS3-2, pp.1-5, Nov. 2020.
16. Takuma Nagao, Ken'ichi Yamaguchi and Hiroshi Iwata: ``Test Plan For Detecting Mersenne Twister Faults In BIST,'' The 23rd Workshop on Synthesis And System Integration of Mixed Information Technologies, R3-5, pp.148-149, Mar. 2021.
17. Chihiro KAGEYAMA, China SASAKI, Hiroshi IWATA, Yosuke ASANO, Yuichi ITOH, Achyut Sapkota, and Ikusaburo KURIMOTO: ``Measurement of Spatial H2O / CO2 Concentration Distribution Around Tomato Plants Using IoT System in Sunlight Type Plant Factory,'' Proceedings of the SICE Annual Conference 2021, pp.937-939, Sep. 2021.

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